Power minimisation during field programmable gate array placement

This study discusses the implementation of two sets of techniques for minimising power within the context of a commercial field programmable gate array (FPGA) placement flow. The first aspect discussed in this work is a power-aware objective function for placement. In particular, a capacitance model for global nets is described which allows the net power in a design to be dramatically reduced. The second aspect describes augmentations to a physical re-synthesis flow, which help to reduce area and power by optimising the number of combinational and sequential cells. The results are quantified across a suite of 119 industrial benchmarks targeting the Actel^?? IGLOO^??FPGA architecture. Power measurements show that the techniques described in this study reduce dynamic power by 13% on average, with a 6.7% average improvement in timing performance across the suite.