DocumentCode :
1486508
Title :
Exploiting the benefits of multiple-path network in DSM systems: architectural alternatives and performance evaluation
Author :
Dai, Donglai ; Panda, Dhabaleswar K.
Author_Institution :
Dept. of Comput. & Inf. Sci., Ohio State Univ., Columbus, OH, USA
Volume :
48
Issue :
2
fYear :
1999
fDate :
2/1/1999 12:00:00 AM
Firstpage :
236
Lastpage :
244
Abstract :
Modern high-performance networks being used for scalable distributed shared-memory (DSM) systems support multiple paths to increase bandwidth and/or reduce contention. Such networks violate the constraint of pairwise in-order message delivery implicitly required by many existing directory-based cache coherence protocols. To solve this problem, two alternative strategies are currently used by computer architects. The first strategy, used in the SGI Origin series, is to employ an intelligent cache coherence protocol which detects and resolves all race conditions caused by out-of-order (OoO) events. The second strategy, used in the HAL Mercury series, is to use a sophisticated network interface (NI) which detects and remedies every OoO event before the messages are fed to the cache coherence controllers. Both strategies involve complicated hardware logic, either at the cache coherence controller level or at the NI level. In this paper, we propose a new strategy that uses block correlated FIFO channels. This new strategy detects all potential race conditions and prevents them from occurring. It allows the use of a simple cache coherence protocol and an inexpensive NI. We also present an efficient implementation of this strategy based on current technology. Detailed simulations are performed using benchmark applications to evaluate the performance of our new strategy. The results indicate that, compared to the existing strategies, our new strategy always provides either the best or close to the best overall performance. This study also provides valuable insights into the design trade-offs in incorporating modern networks into DSM systems
Keywords :
distributed shared memory systems; hazards and race conditions; memory protocols; parallel architectures; performance evaluation; HAL Mercury series; SGI Origin series; benchmark applications; block correlated FIFO channels; complicated hardware logic; intelligent cache coherence protocol; multiple paths; multiple-path network; network interface; race conditions; scalable distributed shared-memory systems; simulations; Access protocols; Coherence; Communication switching; Computer Society; Delay; Event detection; Intelligent networks; Multiprocessor interconnection networks; Network interfaces; Out of order;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.752665
Filename :
752665
Link To Document :
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