System Level Receiver Design for Minimum Sensitivity to Process Variations

A system-level design methodology is proposed to reduce the sensitivity of an integrated zero-IF receiver, including the analog-to-digital converter, to performance variations of its components due to process spreading. Describing each stage of the receiver by three parameters of voltage gain, noise, and nonlinearity, whose variations represent all lower-level sources of variability, the sensitivity of the overall performance to the variations of these parameters is calculated. Three design approaches are proposed, analyzed, and compared for reducing these sensitivities. Statistical and corner simulations are performed to confirm the validity of the proposed guidelines showing significant improvement in the yield of the designs.