Optimizing gate interconnections in four-phase dynamic logic m.o.s. l.s.i. technology

Dynamic logic circuit technology has been used widely to implement large-scale integrated (l.s.i.) circuits using metal-oxide-silicon field effect transistors (m.o.s.f.e.t). One of the factors which determines the overall dimensions of a custom-designed random logic l.s.i. circuit is the number of interconnection tracks as they occupy a large part of the chip between functional modules. This paper describes a multiplexing technique, which allows a reduction in the number of interconnection tracks between modules in l.s.i. circuits implemented using the four-phase dynamic logic technology of the major¿minor configuration. It is shown that the operating speed or performance of the circuit is not affected by this technique.