DocumentCode :
1487216
Title :
Non-Hanan routing
Author :
Hou, Huibo ; Hu, Jiang ; Sapatnekar, Sachin S.
Author_Institution :
Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Volume :
18
Issue :
4
fYear :
1999
fDate :
4/1/1999 12:00:00 AM
Firstpage :
436
Lastpage :
444
Abstract :
This work presents a Steiner tree construction procedure, maximum delay violation Elmore routing tree, to meet specified sink arrival time constraints. It is shown that the optimal tree requires the use of non-Hanan points. The procedure works in two phases: a minimum-delay Steiner Elmore routing tree is first constructed using a minor variant of the Steiner Elmore routing tree procedure, after which the tree is iteratively modified, using an efficient search method, to reduce its length. The search method exploits the piecewise concavity of the delay function to arrive at a solution efficiently. Experimental results show that this procedure works particularly well for technologies where the interconnect resistance dominates, and significant cost savings are shown to be generated
Keywords :
VLSI; circuit optimisation; delays; integrated circuit interconnections; integrated circuit layout; iterative methods; network routing; trees (mathematics); Steiner tree construction procedure; VLSI; delay function; efficient search method; interconnect resistance; iteratively modified tree; maximum delay violation Elmore routing tree; nonHanan routing; piecewise concavity; sink arrival time constraints; Costs; Delay effects; Integrated circuit interconnections; Routing; Search methods; Steiner trees; Time factors; Timing; Topology; Very large scale integration;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.752927
Filename :
752927
Link To Document :
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