Process integration of 3D stacking for backside illuminated image sensor

In this research, a backside illuminated CMOS image sensor (BSI-CIS) without through-silicon via and TSV based Si interposer are developed with thin wafer handling technology. The BSI-CIS wafer is implemented front-side processes then temporary bonded on a Si carrier by using ZoneBOND™ technology. After thinning, the CIS backside is bonded with glass wafer, and the Si carrier is removed using solvent dipping for de-bonding. The thickness of BSI-CIS without TSV is less than 5um, which is visible light transparent to meet the back-side illumination requirement. TSV fabrication, void-free TSV filling, bumping, wafer thinning, thin wafer handling and backside RDL formation are well developed and 30um TSV, 60um thin wafer have been successfully integrated to Si interposer. Cu/Sn bumps with 50μm size are formed with the bump height uniformity less than 5% in wafer level. The wafer-level package of BSI-CIS and TSV based Si interposer have been successfully developed and demonstrated, the characterization results of three layer stacked module is also disclosed in the paper.