• DocumentCode
    1487414
  • Title

    A new division algorithm based on lookahead of partial-remainder (LAPR) for high-speed/low-power coding applications

  • Author

    Kwoon, H.-J. ; Lee, Kwyro

  • Author_Institution
    Korea Adv. Inst. of Sci. & Technol., Taejun, South Korea
  • Volume
    46
  • Issue
    2
  • fYear
    1999
  • fDate
    2/1/1999 12:00:00 AM
  • Firstpage
    202
  • Lastpage
    209
  • Abstract
    A new polynomial division algorithm in finite field GF(2m ) based on the lookahead of partial-remainder (LAPR) is proposed. Since our algorithm is based on partial division on group basis and lookahead technique exploiting the linearity in finite field arithmetic, it is possible to completely eliminate polynomial multiplications leading to highly increased throughput per unit time. The inherent regularity and feedforward nature of our algorithm make it possible to be fully pipelined. When pipelined, its throughput is one quotient and one remainder per clock cycle, regardless of the degree of dividend polynomial, which is orders of magnitude faster than the conventional architecture using linear feedback shift register. An area-efficient sequential architecture based on LAPR is also presented, Although the throughput rate of sequential architecture is lower than that of the pipelined one, it is still higher than that of any division architecture ever reported. They are shown to be efficient, regular, and easily expandable, and hence, naturally suitable for very large scale integration implementation. In systems requiring modest speed, the high-speed nature of our proposed architecture can be traded for low power consumption by reducing clock rate. We verified the general validity of the division algorithm based on LAPR by mathematical manipulation and simulation. The superiority of our proposed architecture compared with other reported ones is demonstrated with regard to its throughput, latency delays, and power
  • Keywords
    Galois fields; computer architecture; delays; digital arithmetic; encoding; pipeline arithmetic; polynomials; area-efficient sequential architecture; finite field arithmetic; high-speed applications; latency delays; lookahead of partial-remainder; low-power coding applications; mathematical manipulation; pipeline architecture; polynomial division algorithm; throughput; Arithmetic; Clocks; Delay; Energy consumption; Galois fields; Linear feedback shift registers; Linearity; Polynomials; Throughput; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1057-7130
  • Type

    jour

  • DOI
    10.1109/82.752954
  • Filename
    752954