DocumentCode :
148745
Title :
Thermal stresses around void in Through Silicon Via in 3D SiP
Author :
Kinoshita, T. ; Sugiura, Toshihiko ; Kawakami, Tomoya ; Matsumoto, Kaname ; Kohara, S. ; Orii, Y.
Author_Institution :
Toyama Prefectural Univ., Toyama, Japan
fYear :
2014
fDate :
23-25 April 2014
Firstpage :
105
Lastpage :
108
Abstract :
Thermal stresses around void in TSV (Through Silicon Via) structure in 3D SiP were discussed under the conditions of device operation and reflow process by using FEM (Finite Element Method). In case of the condition of device operation, equivalent stress around void inside Cu TSV was estimated at around 100 MPa. It showed the low possibility for low cycle fatigue of Cu TSV under device operation because that the stress was lower than yield stress of copper, 210MPa. Maximum principal stress of Si was estimated around 100 MPa. It was lower than bending stress of Si. In case of the condition of reflow process, the equivalent stress of TSV with void was higher than yield stress of Cu. However temperature elevation due to reflow process was once or twice during the process. It showed the low possibility for fracture by low cycle fatigue under reflow process. In case without void, maximum principal stress of Si was estimated around 400 MPa. It was almost similar to the bending strength of Si. Stress concentrations were occurred at parts of corner and interface of materials. It has possibility that singular stress field was formed at the parts, and we should discuss fracture induced by singular stress field.
Keywords :
finite element analysis; reflow soldering; semiconductor device packaging; system-in-package; thermal stress cracking; thermal stresses; three-dimensional integrated circuits; voids (solid); yield stress; 3D SiP; Cu; FEM; Si; TSV low cycle fatigue; TSV structure; bending strength; bending stress; device operation conditions; finite element method; materials interface; maximum principal stress; reflow process; singular stress field; stress concentrations; temperature elevation; thermal stresses around void; three dimensional system in package; through silicon via; yield stress; Semiconductor device modeling; Silicon; Solid modeling; Stress; Thermal stresses; Three-dimensional displays; Through-silicon vias; 3D SiP; FEM(Finite Element Method); TSV(Through Silicon Via); Thermal Stresses; Void;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging (ICEP), 2014 International Conference on
Conference_Location :
Toyama
Print_ISBN :
978-4-904090-10-7
Type :
conf
DOI :
10.1109/ICEP.2014.6826670
Filename :
6826670
Link To Document :
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