Thermal stresses of TSV and Si chip in 3D SiP under device operation and reflow process

The stresses of TSV (Through Silicon Via) and Si chips in 3D-SiP were discussed with a large scale simulator based on FEM (Finite Element Method), ADVENTURECluster. In this study, the stacked layer structure of Si chips is modeled accurately. Thermal stress simulation for TSV structure in Si chips is carried out under thermal loads due to device operation and reflow process. In case of device operation, the equivalent stress of TSV is lower than the yield stress of copper. Maximum principal stress of Si chip is estimated to be around 100MPa. The stress is lower than the bending strength of silicon. However, these stresses level should not be ignored for damage and crack generation of Si single crystals. In case of reflow process, the equivalent stress of TSV at middle part is lower than the yield stress of copper. Maximum principal stress of Si chip is estimated to be around 300MPa. The stress is almost similar the bending strength of silicon.