Vertical and horizontal location design of program voltage generator for 3D-integrated ReRAM/NAND flash hybrid SSD

Author

Ishii, Takuro ; Johguchi, Koh ; Takeuchi, Ken

Author_Institution

Dept. of Electr., Chuo Univ., Tokyo, Japan

fYear

2014

fDate

23-25 April 2014

Firstpage

113

Lastpage

116

Abstract

This paper describes the vertical and horizontal packaging method for Resistive RAM (ReRAM)/NAND flash hybrid SSD. The parasitic effects of vertical and horizontal connections for 3D-hybrid SSD are investigated. The result shows 128 NAND flash memory chips can be stacked considering with V_PGM and V_PASS. In addition, only 4-chip is allowed between ReRAM and the boost converter due to TSV´s parasitic resistance. Also, the length of the horizontal on-interposer wire must be kept less than 3 mm.

Keywords

NAND circuits; electronics packaging; flash memories; power convertors; random-access storage; three-dimensional integrated circuits; wires (electric); 3D-integrated ReRAM; NAND flash hybrid SSD; NAND flash memory chips; TSV parasitic resistance; boost converter; horizontal connections; horizontal location design; horizontal on-interposer wire; horizontal packaging; parasitic effects; program voltage generator; resistive RAM; solid-state drive; vertical connections; vertical location design; vertical packaging; Flash memories; Generators; Memory management; Random access memory; Resistance; Through-silicon vias; Wires; NAND flash; Resistive RAM (ReRAM); boost converter; solid state drive (SSD); through silicon via (TSV);

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Packaging (ICEP), 2014 International Conference on

Conference_Location

Toyama

Print_ISBN

978-4-904090-10-7

Type

conf

DOI

10.1109/ICEP.2014.6826672

Filename

6826672