Title :
Numerical Study of a Highly Scaled Bulk MOSFET With Block Oxide and Source/Drain-Tied Structure
Author :
Eng, Yi-Chuen ; Lin, Jyi-Tsong ; Kuo, Chih-Hao ; Lin, Po-Hsieh ; Fan, Yi-Hsuan ; Chen, Hsuan-Hsu
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
fDate :
5/1/2011 12:00:00 AM
Abstract :
In this paper, we present a highly scaled bulk metal-oxide-semiconductor field-effect transistor with block oxide (BO) and source/drain (S/D)-tied structure that meets the International Technology Roadmap for Semiconductors requirements for high-performance devices. This new device requires only a simple BO fabrication process using SiGe-Si epitaxial growth with selective SiGe removal and requires no additional lithography masks. This proposed BO fabrication process is simple due to it being controllable, repeatable, and fully compatible with standard complementary metal-oxide-semiconductor technology. According to 3-D simulations, our proposed structure not only exhibits its structural advantages to overcome scaling obstacles but also extends the use of planar bulk technology to the decananometer regime.
Keywords :
CMOS integrated circuits; Ge-Si alloys; MOSFET; epitaxial growth; silicon; 3D simulations; BO fabrication process; International Technology Roadmap for Semiconductors; SiGe-Si; block oxide; bulk MOSFET; complementary metal-oxide-semiconductor technology; epitaxial growth; metal-oxide-semiconductor field-effect transistor; planar bulk technology; source/drain-tied structure; Body regions; Fabrication; Leakage current; Logic gates; MOSFET circuits; Semiconductor process modeling; Silicon; Bulk metal–oxide–semiconductor field-effect transistor (MOSFET) with block oxide (BO) and source/drain (S/D)-tied (SDT) structure; decananometer regime; high-performance (HP) devices; standard complementary metal–oxide–semiconductor (CMOS) technology;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2011.2120614