Title :
Challenges of design and packaging for 3D stacking with logic and DRAM dies
Author :
Fukuoka, Kazuki ; Nii, Koji ; Nomura, Tadahiro ; Mori, Ryuhei ; Ochiai, Toshihiko ; Takayanagi, Kota ; Mori, Kazuo ; Kida, T. ; Morita, S.
Author_Institution :
Renesas Electron. Corp., Kodaira, Japan
Abstract :
A Wide IO DRAM controller chip with Through Silicon Via (TSV) technology is implemented. Test circuitry for prebonding TSV tests are embedded in between the fine pitch TSVs. In order to reduce Vmin degradation induced by 512 DQs simultaneously switching noise, we introduce a package-board impedance optimization method utilizing a full digital noise monitor. We also develop a 3D stacked flip chip assembly process with void less underfill enabled by Non Conductive Film (NCF). 12.8 GB/s operation is achieved, while IO power was reduced by 89% compared to LPDDR3.
Keywords :
DRAM chips; flip-chip devices; logic design; logic devices; three-dimensional integrated circuits; 3D stacking; DRAM dies; digital noise monitor; flip chip assembly process; logic dies; non conductive film; package board impedance optimization method; test circuitry; through silicon via technology; wide IO DRAM controller chip; Bonding; Monitoring; Noise; Random access memory; Stacking; Three-dimensional displays; Through-silicon vias; 3D stacking; TSV; Wide IO DRAM; fully digital noise monitor; impedance optimization; pre-bonding test; switching noise; thermal issues; void less underfill;
Conference_Titel :
Electronics Packaging (ICEP), 2014 International Conference on
Conference_Location :
Toyama
Print_ISBN :
978-4-904090-10-7
DOI :
10.1109/ICEP.2014.6826722
