Title :
System-on-chip testability using LSSD scan structures
Author :
Zarrineh, Kamran ; Upadhyaya, Shambhu J. ; Chickermane, Vivek
Author_Institution :
Sun Microelectron., Chelmsford, MA, USA
fDate :
5/1/2001 12:00:00 AM
Abstract :
A technology-independent test synthesis tool extends the basic level-sensitive scan design (LSSD) boundary scan methodology. It reuses functional storage elements wherever possible and introduces minimal test logic overhead and delay
Keywords :
boundary scan testing; integrated circuit testing; LSSD scan structures; boundary scan; level-sensitive scan design; storage elements; technology-independent; test synthesis tool; Automatic testing; Clocks; Flip-flops; Logic testing; Master-slave; Microelectronics; Protocols; Shift registers; System testing; System-on-a-chip;
Journal_Title :
Design & Test of Computers, IEEE
