Title :
Package on package DDR Power Integrity Design
Author :
Heng Chuan Shu ; Li Chuang Quek
Author_Institution :
Intel Microelectron. Malaysia, Minden, Malaysia
Abstract :
The IC (integrated circuit) packaging technology has evolved and transitioned from wirebond to flipchip, multi-chip package (MCP) to 3D stacking. PoP (Package on Package) enables the vertical integration of memory on the conventional package which helps to achieve higher component density on the platform. PoP technology is very important for modern electronics devices as it features more function in very compact devices such as smart phones and tablets. While PoP offers denser component count on platform, it also comes with electrical challenges such as Power Integrity issue. Conventional Power Integrity Design and Methodology may not hold for PoP technology.
Keywords :
DRAM chips; integrated circuit design; integrated circuit packaging; DDR power integrity design; integrated circuit packaging technology; package on package; vertical integration; Capacitance; Impedance; Inductance; Noise; Random access memory; Stability analysis; System-on-chip; DDR; Package on package (PoP); System On Chip (SoC); power delivery;
Conference_Titel :
Electronics Packaging (ICEP), 2014 International Conference on
Conference_Location :
Toyama
Print_ISBN :
978-4-904090-10-7
DOI :
10.1109/ICEP.2014.6826741