Title :
Fixed-State Tests for Delay Faults in Scan Designs
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
One of the methods to reduce the power dissipation during scan shifting is based on holding the state inputs to the combinational logic of a circuit constant for the duration of a scan operation. We note that this method also allows a new type of two-pattern scan-based tests to be applied. We refer to these tests as fixed-state tests. These tests have several properties that make them effective as complements to skewed-load and broadside tests, and also allows them to be computed efficiently. We discuss these properties in the context of transition faults. We describe procedures for selecting the constant vector for the state inputs during a scan operation, and for generating fixed-state tests. We present experimental results to demonstrate the transition fault coverage improvements possible with these tests.
Keywords :
circuit testing; logic circuits; logic testing; broad-side test; delay faults; fixed-state tests; power dissipation; scan designs; scan operation; skewed-load test; transition fault coverage improvements; two-pattern scan-based tests; Circuit faults; Circuit testing; Combinational circuits; Delay; Design methodology; Electrical fault detection; Fault detection; Logic testing; Power dissipation; Power engineering computing; Broadside tests; power dissipation; scan design; skewed-load tests; transition faults;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2009.2030811