Title :
Low-power clock-deskew buffer for high-speed digital circuits
Author :
Liu, Shen-Iuan ; Lee, Jiunn-Hwa ; Tsao, Hen-Wai
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
4/1/1999 12:00:00 AM
Abstract :
An IC containing four clock deskew buffers using the delay-locked-loop technology has been fabricated in a 0.6 μm single poly double metal CMOS process. The core chip area is 0.9×0.9 mm 2. The maximum operating frequency is 80 MHz, and the total power dissipation of the four deskew buffers is 59 mW for a 3 V supply voltage. The maximum clock skew after deskewing is less than 300 ps, and the peak-to-peak clock jitter is less than 170 ps. The deskew range is 0.5-3.8 ns
Keywords :
CMOS integrated circuits; buffer circuits; delay lock loops; digital circuits; low-power electronics; mixed analogue-digital integrated circuits; timing; 0.6 micron; 3 V; 59 mW; 80 MHz; DLL technology; delay-locked-loop technology; high-speed digital circuits; low-power clock-deskew buffer; single poly double metal CMOS process; CMOS integrated circuits; CMOS process; CMOS technology; Clocks; Delay; Digital circuits; Frequency; Jitter; Power dissipation; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
