Title :
A register-controlled symmetrical DLL for double-data-rate DRAM
Author :
Lin, Feng ; Miller, Jason ; Schoenfeld, Aaron ; Ma, Manny ; Baker, R. Jacob
Author_Institution :
Microelectron. Res. Center, Idaho Univ., Boise, ID, USA
fDate :
4/1/1999 12:00:00 AM
Abstract :
This paper describes a register-controlled symmetrical delay-locked loop (RSDLL) for use in a high-frequency double-data-rate DRAM. The RSDLL inserts an optimum delay between the clock input buffer and the clock output buffer, making the DRAM output data change simultaneously with the rising or falling edges of the input clock. This RSDLL is shown to be insensitive to variations in temperature, power-supply voltage, and process after being fabricated in 0.21 μm CMOS technology. The measured r.m.s. jitter is below 50 ps when the operating frequency is in the range of 125-250 MHz
Keywords :
CMOS memory circuits; DRAM chips; delay lock loops; high-speed integrated circuits; 0.21 micron; 125 to 250 MHz; CMOS technology; clock input buffer; clock output buffer; double-data-rate DRAM; high-frequency DRAM; optimum delay insertion; register-controlled symmetrical DLL; symmetrical delay-locked loop; CMOS technology; Clocks; Delay effects; Delay lines; Frequency; Random access memory; SDRAM; Shift registers; Temperature; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
