• DocumentCode
    1489247
  • Title

    A simple voltage scaling formula for low-power CMOS circuits

  • Author

    Kang, Dae-Gwan ; Park, Young June ; Min, Hong Shick

  • Author_Institution
    Sch. of Electr. Eng., Seoul Nat. Univ., South Korea
  • Volume
    46
  • Issue
    4
  • fYear
    1999
  • fDate
    4/1/1999 12:00:00 AM
  • Firstpage
    803
  • Lastpage
    805
  • Abstract
    A simple formula is proposed for the analysis of the gate delay of CMOS gate under low VDD. The effects of device parameters on gate delay and energy are readily obtained using the formula. Thus, it has the potential for use in the design of device parameters in the low VDD CMOS circuits
  • Keywords
    CMOS integrated circuits; delays; integrated circuit design; network analysis; gate delay; low-power CMOS circuits; voltage scaling formula; Delay effects; Equations; Inverters; Low voltage; MOSFET circuits; Semiconductor device modeling; Threshold voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.753718
  • Filename
    753718
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1489247