Title :
The design of a one megabit non-volatile M-R memory chip using 1.5×5 μm cells
Author :
Pohm, A.V. ; Huang, J.S.T. ; Daughton, J.M. ; Krahn, D.R. ; Mehra, V.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
fDate :
11/1/1988 12:00:00 AM
Abstract :
A 106-bit chip has been designed using 1.5-μm magnetoresistive double-layer memory elements and bipolar circuitry. The bipolar circuitry is based on nominal 1.25-μm optical lithography. The total chip area of the design is 8.5 mm×9.5 mm. To enhance the signal-to-noise ratio, multiple reads are used with the nondestructive readout cells. Design read time is 3 μs. Design write time is 0.2 μs. The design includes three redundant, fuse-selectable sense lines for each group of 32 sense lines. If the bit failure rate is 0.0005 or less, yield loss for the 106-bit chip due to sense line failure is less than 19%. With improved lithography, elements as small as 0.75 μm×2.5 μm could be made from the material
Keywords :
bipolar integrated circuits; integrated memory circuits; magnetic film stores; magnetoresistance; 0.2 mus; 1 Mbit; 3 mus; bipolar circuitry; bit failure rate; fuse-selectable sense lines; magnetoresistive double-layer memory elements; memory chip; multiple reads; nondestructive readout cells; optical lithography; read time; signal-to-noise ratio; write time; yield loss; Bars; Integrated circuit technology; Lithography; Magnetic analysis; Magnetic materials; Nonvolatile memory; Optical arrays; Optical noise; Optical sensors; Semiconductor materials;
Journal_Title :
Magnetics, IEEE Transactions on
