• DocumentCode
    1490773
  • Title

    A Flexible Parallel Hardware Architecture for AdaBoost-Based Real-Time Object Detection

  • Author

    Kyrkou, Christos ; Theocharides, Theocharis

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Cyprus, Nicosia, Cyprus
  • Volume
    19
  • Issue
    6
  • fYear
    2011
  • fDate
    6/1/2011 12:00:00 AM
  • Firstpage
    1034
  • Lastpage
    1047
  • Abstract
    Real-time object detection is becoming necessary for a wide number of applications related to computer vision and image processing, security, bioinformatics, and several other areas. Existing software implementations of object detection algorithms are constrained in small-sized images and rely on favorable conditions in the image frame to achieve real-time detection frame rates. Efforts to design hardware architectures have yielded encouraging results, yet are mostly directed towards a single application, targeting specific operating environments. Consequently, there is a need for hardware architectures capable of detecting several objects in large image frames, and which can be used under several object detection scenarios. In this work, we present a generic, flexible parallel architecture, which is suitable for all ranges of object detection applications and image sizes. The architecture implements the AdaBoost-based detection algorithm, which is considered one of the most efficient object detection algorithms. Through both field-programmable gate array emulation and large-scale implementation, and register transfer level synthesis and simulation, we illustrate that the architecture can detect objects in large images (up to 1024 × 768 pixels) with frame rates that can vary between 64-139 fps for various applications and input image frame sizes.
  • Keywords
    field programmable gate arrays; object detection; parallel architectures; AdaBoost-based real-time object detection; FPGA; bioinformatics; computer vision; field-programmable gate array emulation; flexible parallel hardware architecture; image processing; large-scale implementation; register transfer level synthesis; Application software; Bioinformatics; Computer architecture; Computer security; Computer vision; Hardware; Image processing; Object detection; Parallel architectures; Software algorithms; Object detection; VLSI; systolic arrays;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2010.2048224
  • Filename
    5464392