Title :
DIVA: dual-issue VLIW architecture with media instructions for image processing
Author :
Nam, Sang-Joon ; Kwon, Young-Su ; Im, Yeon-Ho ; Kang, Kyung-Ku ; Kyung, Chong-Min
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
fDate :
2/1/1999 12:00:00 AM
Abstract :
According to the demand on enormous multimedia data processing, we have designed a VLIW (very long instruction word) processor called DIVA (dual-issue VLIW architecture) exploiting the ILP (instruction-level parallelism) in multimedia programs. The DIVA processor which can execute two instructions in one cycle supports 86 instructions including 30 media instructions, and has a sub-word execution structure that supports the saturation mode arithmetic for image processing. Compared to scalar architectures without media instructions, the performance of the DIVA processor is improved by 2.2 to 5 times due to the combination of the VLIW architecture and media instructions. The DIVA processor, consisting of about 90,000 gates, was implemented using the 0.6 μm CMOS SOG (sea-of-gate) process on a 8 mm×8 mm die, and has shown a performance of 80 MOPS (million operations per second) at 10 MHz clock frequency
Keywords :
CMOS digital integrated circuits; digital signal processing chips; image processing; integrated circuit design; parallel architectures; 0.6 micron; 10 MHz; CMOS SOG process; DIVA; ILP; dual-issue VLIW architecture; image processing; instruction-level parallelism; media instructions; multimedia data processing; multimedia programs; performance; saturation mode arithmetic; sea-of-gate process; sub-word execution structure; very long instruction word processor; Arithmetic; CMOS process; Clocks; Data processing; Graphics; Image processing; Multimedia systems; Pixel; Process design; VLIW;
Journal_Title :
Consumer Electronics, IEEE Transactions on
