CMOS Inverter Based on Schottky Source–Drain MOS Technology With Low-Temperature Dopant Segregation

Author

Larrieu, Guilhem ; Dubois, Emmanuel

Author_Institution

CNRS, Univ. de Toulouse, Toulouse, France

Volume

32

Issue

6

fYear

2011

fDate

6/1/2011 12:00:00 AM

Firstpage

728

Lastpage

730

Abstract

This letter demonstrates the integration of complementary dopant-segregated Schottky barrier MOSFETs into CMOS inverters. The implementation of a valence-band-edge silicide, namely, PtSi, associated to arsenic (As) and boron (B) low-temperature segregation is validated for the first time at the circuit level. Current drives for n- and p-type devices are I_on = 596/378 μA/μm at V_ds = |1.1 V| and |V_gs| = 2 V to account for the 2.4-nm gate oxide thickness. Excellent inverter voltage transfer characteristics, large voltage gain, and appreciable noise margins have been obtained down to 0.5 V of supply voltage.

Keywords

CMOS logic circuits; MOSFET circuits; Schottky diodes; logic gates; platinum compounds; CMOS inverters; PtSi; Schottky source-drain MOS technology; complementary dopant-segregated Schottky barrier MOSFET; low-temperature dopant segregation; low-temperature segregation; valence-band-edge silicide; voltage 0.5 V; wavelength 2.4 nm; CMOS integrated circuits; Inverters; Logic gates; MOSFETs; Schottky barriers; Silicides; CMOS inverter; MOSFETs; Schottky barrier (SB); dopant segregation (DS); silicon-on-insulator (SOI);

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2011.2131111

Filename

5746498