A 10 b 50 MHz 320 mW CMOS A/D converter for video applications

Author

Jeon, Byeong-Lyeol ; Lee, Seung-Hoon

Author_Institution

Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea

Volume

45

Issue

1

fYear

1999

fDate

2/1/1999 12:00:00 AM

Firstpage

252

Lastpage

258

Abstract

This paper describes a 10b 50 MHz CMOS analog-to-digital converter (ADC) for high-speed signal processing applications. The proposed pipelined ADC adopts a selective channel-length adjustment technique for current mismatch minimization, a switched bias technique for power reduction of high-speed op amps, and a capacitor scaling technique for reduced power and chip area. The measured differential and integral nonlinearities of the prototype in a 0.8 μm CMOS show less than ±0.6 LSB and ±2.0 LSB, respectively. The typical power consumption is 119 mW at 3 V and 40 MHz, and 320 mW at 5 V and 50 MHz

Keywords

CMOS digital integrated circuits; analogue-digital conversion; digital signal processing chips; video signal processing; 0.8 micron; 10 bit; 119 mW; 3 V; 320 mW; 40 MHz; 5 V; 50 MHz; CMOS A/D converter; LSB; analog-to-digital converter; capacitor scaling; high speed signal processing; high-speed op amps; high-speed signal processing applications; measured differential nonlinearity; measured integral nonlinearity; mismatch minimization; pipelined ADC; power consumption; power reduction; reduced chip area; reduced power; selective channel-length adjustment; switched bias technique; video applications; Analog-digital conversion; CMOS technology; Capacitors; Circuit synthesis; Clocks; Energy consumption; Logic; Operational amplifiers; Prototypes; Voltage;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.754443

Filename

754443