On hardware implementation of the split-radix FFT

An algorithm for computing length-2^M discrete Fourier transforms (DFTs), called the split-radix FFT, has recently been developed. The split-radix algorithm has fewer multiplies than the radix-8 Cooley-Tukey algorithm, and many fewer additions that the minimum-multiply algorithms. It is shown that it involves significantly more butterfly computations than the radix-4 Cooley-Tukey algorithms which have butterflies of similar complexity. Consequently, the split-radix algorithm is advantageous for hardware in which a multiplier/accumulator is the basic processor, as might be the case with some VLSI implementations. In addition, the split-radix algorithm has varying numbers of butterflies in successive stages, complicating the design of efficient multiprocessor implementations. A few simple strategies for balancing the computational load among the stages are considered, and their average efficiencies are computed