Title :
64-bit carry-select adder with reduced area
Author :
Kim, Youngjoon ; Kim, Lee-Sup
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
fDate :
5/10/2001 12:00:00 AM
Abstract :
A carry-select adder can be implemented by using a single ripple-carry adder and an add-one circuit instead of using dual ripple-carry adders. A multiplexer-based add-one circuit is proposed to reduce the area with negligible speed penalty. The proposed 64 bit carry-select adder requires 42% fewer transistors than the conventional carry-select adder
Keywords :
adders; carry logic; multiplexing equipment; 64 bit; carry-select adder; multiplexer-based add-one circuit; ripple-carry adder; speed penalty;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20010430
