DocumentCode
1492179
Title
A 4K Josephson memory
Author
Suzuki, H. ; Fujimaki, N. ; Tamura, H. ; Imamura, T. ; Hasuo, S.
Author_Institution
Fujitsu Ltd., Atsugi, Japan
Volume
25
Issue
2
fYear
1989
fDate
3/1/1989 12:00:00 AM
Firstpage
783
Lastpage
788
Abstract
The authors describe the design and experimental performance of a 4 K×1-bit Josephson (RAM). For high-speed memory operation, the authors have developed a compact AND gate for the decoder, a high-voltage driver gate, and a capacitively coupled single-flux quantum memory cell. The 4 K memory was designed using these gates and cell and was fabricated with Nb/AlOx/Nb junctions. The minimum access time was 590 ps, and the total power dissipation was 19 mW
Keywords
aluminium compounds; integrated circuit technology; integrated memory circuits; niobium; random-access storage; superconducting junction devices; superconducting memory circuits; 19 mW; 4 kbit; 590 ps; AND gate; Josephson memory; Nb-AlOx-Nb junctions; RAM; access time; capacitively coupled single-flux quantum memory cell; experimental performance; high-speed memory operation; high-voltage driver gate; power dissipation; Decoding; Equivalent circuits; Josephson junctions; Logic gates; Niobium; Power dissipation; Power measurement; Time measurement; Timing; Voltage;
fLanguage
English
Journal_Title
Magnetics, IEEE Transactions on
Publisher
ieee
ISSN
0018-9464
Type
jour
DOI
10.1109/20.92404
Filename
92404
Link To Document