A physical design tool for built-in self-repairable RAMs

Author

Chakraborty, Kanad ; Kulkami, S. ; Bhattacharya, Mayukh ; Mazumder, Pinaki ; Gupta, Anurag

Author_Institution

EDA Lab., IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

9

Issue

2

fYear

2001

fDate

4/1/2001 12:00:00 AM

Firstpage

352

Lastpage

364

Abstract

In this paper, we present the description and evaluation of a novel physical design tool, BISRAMGEN, that can generate reconfigurable and fault-tolerant RAM modules. This tool designs a redundant RAM array with accompanying built-in self-test (BIST) and built-in self-repair (BISR) logic that can switch out faulty rows and switch in spare rows. Built-in self-repair causes significant improvement in reliability, production yield, and manufacturing cost of ASICs and microprocessors with embedded RAMs.

Keywords

application specific integrated circuits; built-in self test; fault tolerance; integrated circuit design; integrated circuit reliability; integrated circuit yield; random-access storage; reconfigurable architectures; redundancy; BISRAMGEN; built-in self-repairable RAMs; fault-tolerant RAM modules; faulty rows; manufacturing cost; physical design tool; production yield; reconfigurable RAM modules; redundant RAM array; reliability; spare rows; Built-in self-test; Costs; Fault tolerance; Logic arrays; Logic design; Manufacturing; Microprocessors; Production; Reconfigurable logic; Switches;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/92.924057

Filename

924057