Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits

Author

Pant, Pankaj ; Roy, Rabindra K. ; Chattejee, A.

Author_Institution

Compaq Comput. Corp., Shrewsbury, MA, USA

Volume

9

Issue

2

fYear

2001

fDate

4/1/2001 12:00:00 AM

Firstpage

390

Lastpage

394

Abstract

We demonstrate a novel algorithm for assigning the threshold voltage to the gates in a digital random logic complementary metal-oxide-semiconductor (CMOS) circuit for a dual-threshold voltage process. The tradeoff between static and dynamic power consumption has been explored. When used along with device sizing and supply voltage reduction techniques for low power, the proposed algorithm can reduce the total power dissipation of a circuit by as much as 50%.

Keywords

CMOS logic circuits; VLSI; circuit CAD; circuit optimisation; integrated circuit design; logic CAD; low-power electronics; CMOS; device sizing; digital random logic; dual-threshold voltage assignment; dynamic power consumption; low power CMOS circuits; static power consumption; supply voltage reduction; total power dissipation; transistor sizing; CMOS digital integrated circuits; CMOS logic circuits; CMOS process; Consumer electronics; Energy consumption; Logic devices; Power dissipation; Threshold voltage; Very large scale integration; Wireless communication;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/92.924061

Filename

924061