DocumentCode
1492457
Title
Long unsigned number systolic serial multipliers and squarers
Author
Pekmestzi, K.Z. ; Kalivas, P. ; Moshopoulos, N.
Author_Institution
Dept. of Electr. & Comput. Eng., Nat. Tech. Univ. of Athens, Greece
Volume
48
Issue
3
fYear
2001
fDate
3/1/2001 12:00:00 AM
Firstpage
316
Lastpage
321
Abstract
A systolic serial multiplier and a squarer for unsigned numbers which operate without zero words inserted between successive data words, output the full product, and have only one clock cycle latency-are presented. The multiplier is based on a modified serial/parallel scheme that operates with 100% efficiency. The systolic form is obtained by merging two adjacent multiplier cells. The same technique is used for the design of a serial squarer. The systolisity and the continuous operation are achieved without an increase in hardware complexity. The proposed schemes are well suited for long number multiplication and squaring
Keywords
multiplying circuits; systolic arrays; 100 percent; long unsigned number; serial multiplier; serial squarer; systolic circuit; Arithmetic; Circuits; Clocks; Computer architecture; Cryptography; Delay; Hardware; Merging; Pipelines; Wiring;
fLanguage
English
Journal_Title
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
Publisher
ieee
ISSN
1057-7130
Type
jour
DOI
10.1109/82.924075
Filename
924075
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