Title :
Long unsigned number systolic serial multipliers and squarers
Author :
Pekmestzi, K.Z. ; Kalivas, P. ; Moshopoulos, N.
Author_Institution :
Dept. of Electr. & Comput. Eng., Nat. Tech. Univ. of Athens, Greece
fDate :
3/1/2001 12:00:00 AM
Abstract :
A systolic serial multiplier and a squarer for unsigned numbers which operate without zero words inserted between successive data words, output the full product, and have only one clock cycle latency-are presented. The multiplier is based on a modified serial/parallel scheme that operates with 100% efficiency. The systolic form is obtained by merging two adjacent multiplier cells. The same technique is used for the design of a serial squarer. The systolisity and the continuous operation are achieved without an increase in hardware complexity. The proposed schemes are well suited for long number multiplication and squaring
Keywords :
multiplying circuits; systolic arrays; 100 percent; long unsigned number; serial multiplier; serial squarer; systolic circuit; Arithmetic; Circuits; Clocks; Computer architecture; Cryptography; Delay; Hardware; Merging; Pipelines; Wiring;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on