The TX1 32-bit microprocessor: performance analysis, and debugging support

Author

Miyata, M. ; Kishigami, H. ; Okamoto, Kosei ; Kamiya, Shigeo

Author_Institution

Toshiba Corp., Saiwaiku, Japan

Volume

8

Issue

2

fYear

1988

fDate

4/1/1988 12:00:00 AM

Firstpage

37

Lastpage

46

Abstract

The 32-bit TX1 microprocessor, developed to meet the architectural specification of Japan´s TRON (The Real-Time-Operating Nucleus) project, has been given a loosely coupled pipeline structure to meet the demands of high-performance systems. The authors discuss the design architecture of the TX1, provide some performance analysis for the design, and describe the debugging feature provided on the processor. Results for several benchmark programs show that the average performance of the TX1 is over 5 MIPS (million instructions per second).<>

Keywords

computer architecture; microprocessor chips; performance evaluation; program debugging; research initiatives; 32 bit; 32-bit TX1 microprocessor; 5 MIPS; Japan; TRON; The Real-Time-Operating Nucleus; Toshiba; benchmark programs; debugging support; loosely coupled pipeline structure; performance analysis; Computer architecture; Debugging; Intelligent robots; Memory management; Microprocessors; Operating systems; Performance analysis; Pipelines; Real time systems; Registers;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/40.528

Filename

528