Reconfigurable SRAM Architecture With Spatial Voltage Scaling for Low Power Mobile Multimedia Applications

Author

Cho, Minki ; Schlessman, Jason ; Wolf, Wayne ; Mukhopadhyay, Saibal

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

Volume

19

Issue

1

fYear

2011

Firstpage

161

Lastpage

165

Abstract

This paper presents a dynamically reconfigurable SRAM array for low-power mobile multimedia application. The proposed structure use a lower voltage for cells storing low-order bits and a nominal voltage for cells storing higher order bits. The architecture allows reconfigure the number of bits in the low-voltage mode to change the error characteristics of the array in run-time. Simulations in predictive 70 nm nodes show that the proposed array can obtain 45% savings in memory power with a marginal (~10%) reduction in image quality.

Keywords

SRAM chips; image processing; low-power electronics; reconfigurable architectures; cell storing low-order bits; image quality; low power mobile multimedia applications; low-order bits; memory power; reconfigurable SRAM architecture; reconfigurable SRAM array; spatial voltage scaling; wavelength 70 nm; Bit error rate; Degradation; Energy efficiency; Image quality; Low voltage; Multimedia systems; Pixel; Predictive models; Random access memory; Runtime; Image processing; Low-power; SRAM; multimedia; process variations; reconfiguration;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2009.2031468

Filename

5280187