Systolic architectures for vector quantization

Author

Davidson, Grant A. ; Cappello, Peter R. ; Gersho, Allen

Volume

36

Issue

10

fYear

1988

fDate

10/1/1988 12:00:00 AM

Firstpage

1651

Lastpage

1664

Abstract

A family of architectural techniques are proposed which offer efficient computation of weighted Euclidean distance measures for nearest-neighbor codebook searching. The general approach uses a single metric comparator chip in conjunction with a linear array of inner product processor chips. Very high vector-quantization (VQ) throughout can be achieved for many speech and image-processing applications. Several alternative configurations allow reasonable tradeoffs between speed and VLSI chip area required

Keywords

cellular arrays; computer architecture; data compression; encoding; picture processing; speech analysis and processing; VLSI chip area; codebook searching; data compression; image-processing; inner product processor chips; linear array; single metric comparator chip; speech processing; speed; systolic architecture; vector quantisation; weighted Euclidean distance; Computer architecture; Data compression; Euclidean distance; Laboratories; Pattern recognition; Speech processing; Speech recognition; Throughput; Vector quantization; Very large scale integration;

fLanguage

English

Journal_Title

Acoustics, Speech and Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

0096-3518

Type

jour

DOI

10.1109/29.7553

Filename

7553