Title :
New CMOS realization of the CCII-
Author :
Awad, I.A. ; Soliman, A.M.
Author_Institution :
Dept. of Electron. & Commun. Eng., Cairo Univ., Giza, Egypt
fDate :
4/1/1999 12:00:00 AM
Abstract :
New second-generation current conveyor negative (CCII-) realization suitable for very large scale implementation is described. The proposed architecture provides a very low impedance level at the N terminal and a wide dynamic voltage range, as well as a high current tracking accuracy. Simulations show that the CCII- current follower bandwidth extends beyond 100 MHz. Two compensation methods are discussed: the first results in voltage-offset cancellation, while the second results in voltage-offset compensation as well as Rx reduction
Keywords :
CMOS analogue integrated circuits; VLSI; current conveyors; 100 MHz; CCII-; CMOS chip; VLSI architecture; compensation; second-generation current conveyor negative; simulation; Bandwidth; CMOS technology; Circuits; Dynamic range; Dynamic voltage scaling; Frequency response; Impedance; Large-scale systems; Mirrors; Transconductance;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
