An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling

This letter introduces an analytical model to represent line-edge roughness (LER) effects on both off-state leakage and drive current for sub-100-nm devices. The model partitions a given device into small unit cells along its width, each unit cell assumes a constant gate length (i.e., cell´s width is small compared to LER spatial frequency). An analytical model is used to represent saturated threshold voltage dependency on the unit cell´s gate length. Using this technique, an efficient and accurate model for LER effects (through V/sub ts/ variations) on off-state leakage and drive current is proposed and experimentally validated using 193 and 248 nm lithography for devices with 80-nm nominal gate lengths. Assuming that the deviation from the ideal 0-LER case remains constant from generation to generation, the model predicts that 3 nm or less LER is required for 50-60-nm state-of-the-art devices in the 0.1-μm technology node. Based on data presented, we suggest that the LER requirement for this technology node is attainable with an alternated phase-shift type of patterning process.