Title :
A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator
Author :
Sun, Lizhong ; Kwasniewski, Tadeusz A.
Author_Institution :
Lucent Technols., Allentown, PA, USA
fDate :
6/1/2001 12:00:00 AM
Abstract :
A general ring oscillator topology for multiphase outputs is presented and analyzed. The topology uses the interpolating inverter stages to construct fast subfeedback loops for long chain rings to obtain both multiphase outputs and higher speed operation. There exists an optimum number of inverter stages inside a subfeedback loop which gives the highest oscillation frequency. A fully integrated 1.25-GHz 0.35-μm CMOS phase-locked-loop clock generator that incorporates the proposed voltage-controlled oscillator topology was designed and implemented for a data transceiver. It provides eight-phase outputs and achieves RMS tracking jitter of 11 ps from a 3.3-V power supply
Keywords :
CMOS analogue integrated circuits; UHF integrated circuits; UHF oscillators; circuit feedback; frequency synthesizers; phase locked loops; voltage-controlled oscillators; 0.35 micron; 1.25 GHz; 11 ps; 3.3 V; RMS tracking jitter; data transceiver; eight-phase outputs; interpolating inverter stages; inverter stages; long chain rings; monolithic CMOS PLL; multiphase ring oscillator; oscillation frequency; subfeedback loop; subfeedback loops; voltage-controlled oscillator topology; Clocks; Frequency; Inverters; Jitter; Phase locked loops; Power supplies; Ring oscillators; Topology; Transceivers; Voltage-controlled oscillators;
Journal_Title :
Solid-State Circuits, IEEE Journal of
