CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices

Author

González, Alejandro F. ; Bhattacharya, Mayukh ; Kulkarni, Shriram ; Mazumder, Pinaki

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA

Volume

36

Issue

6

fYear

2001

fDate

6/1/2001 12:00:00 AM

Firstpage

924

Lastpage

932

Abstract

This paper presents a fully integrated implementation of a multivalued-logic signed-digit full adder (SDFA) circuit using a standard 0.6-μm CMOS process. The radix-2 SDFA circuit, based on two-peak negative-differentiaI-resistance (NDR) devices, has been implemented using MOS-NDR, a new prototyping technique for circuits that combine MOS transistors and NDR devices. In MOS-NDR, the folded current-voltage characteristics of NDR devices such as resonant-tunneling diodes (RTDs) are emulated using only nMOS transistors. The SDFA prototype has been fabricated and correct function has been verified. With an area of 123.75 by 38.7 μm² and a simulated propagation delay of 17 ns, the MOS-NDR prototype is more than 15 times smaller and slightly faster than the equivalent hybrid RTD-CMOS implementation

Keywords

CMOS logic circuits; adders; delays; multivalued logic circuits; negative resistance circuits; resonant tunnelling diodes; 0.6 micron; 17 ns; CMOS implementation; MOS-NDR; folded current-voltage characteristics; multiple-valued logic signed-digit full adder; radix-2 SDFA circuit; resonant-tunneling diodes; simulated propagation delay; two-peak negative-differentiaI-resistance devices; Adders; CMOS logic circuits; CMOS process; Current-voltage characteristics; Diodes; Logic devices; MOSFETs; Propagation delay; Prototypes; Resonant tunneling devices;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.924855

Filename

924855