Title :
A 7.1-GB/s low-power rendering engine in 2-D array-embedded memory logic CMOS for portable multimedia system
Author :
Park, Yong-Ha ; Han, Seon-Ho ; Lee, Jung-Hwan ; Yoo, Hoi-Jun
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
fDate :
6/1/2001 12:00:00 AM
Abstract :
A single-chip rendering engine that consists of a DRAM frame buffer, a SRAM serial access memory, pixel/edge processor array and 32-b RISC core is proposed for low-power three-dimensional (3-D) graphics in portable systems. The main features are two-dimensional (2-D) hierarchical octet tree (HOT) array structure with bandwidth amplification, three dedicated network schemes, virtual page mapping, memory-coupled logic pipeline, low-power operation, 7.1-GB/s memory bandwidth, and 11.1-Mpolygon/s drawing speed. The 56-mm2 prototype die integrating one edge processor, eight pixel processors, eight frame buffers, and a RISC core are fabricated using 0.35-μm CMOS embedded memory logic (EML) technology with four poly layers and three metal layers. The fabricated test chip, 590 mW at 100 MHz 3.3 V operation, is demonstrated with a host PC through a PCI bridge
Keywords :
CMOS digital integrated circuits; VLSI; computer graphic equipment; high-speed integrated circuits; low-power electronics; microprocessor chips; multimedia computing; parallel architectures; pipeline processing; reduced instruction set computing; rendering (computer graphics); solid modelling; 0.35 micron; 100 MHz; 2D array-embedded memory logic CMOS; 2D hierarchical octet tree array structure; 3.3 V; 32 bit; 590 mW; 7.1 GB/s; DRAM frame buffer; RISC core; SRAM serial access memory; bandwidth amplification; dedicated network schemes; edge processor; graphics chip; low-power 3D graphics; low-power rendering engine; memory-coupled logic pipeline; pixel processors; pixel/edge processor array; portable multimedia system; single-chip rendering engine; virtual page mapping; Bandwidth; CMOS logic circuits; Engines; Graphics; Logic arrays; Random access memory; Reduced instruction set computing; Rendering (computer graphics); Tree graphs; Two dimensional displays;
Journal_Title :
Solid-State Circuits, IEEE Journal of
