Title :
A 14-b 20-Msamples/s CMOS pipelined ADC
Author :
Chen, Hsin-Shu ; Song, Bang-Sup ; Bacrania, Kantilal
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
fDate :
6/1/2001 12:00:00 AM
Abstract :
The capacitor error-averaging technique, updated with look-ahead decision and digital correction, is used to demonstrate a 14-b 20-Msamples/s pipelined analog-to digital converter (ADC) with no trimming or calibration. The prototype ADC exhibits a differential nonlinearity (DNL) of +0.23/-0.28 least significant bit (LSB), an integral nonlinearity (INL) of +0.95/-1.06 LSB, a spurious-free dynamic range (SFDR) of 91.6 dB, and a signal-to-noise ratio (SNR) of 74.2 dB with a 1-MHz input and a 20-MHz clock. The prototype in 0.5-μm CMOS occupies an area of 4.5×2.4 mm2 and consumes 720 mW at 5 V
Keywords :
CMOS integrated circuits; analogue-digital conversion; errors; high-speed integrated circuits; pipeline processing; 0.5 micron; 14 bit; 20 MHz; 5 V; 720 mW; 74.2 dB; A/D convertor; CMOS pipelined ADC; DNL; INL; SNR; analog-to digital converter; capacitor error-averaging technique; differential nonlinearity; digital correction; integral nonlinearity; look-ahead decision; signal-to-noise ratio; Analog-digital conversion; Calibration; Capacitors; Clocks; Dynamic range; Error correction; Feedback; Operational amplifiers; Prototypes; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
