A new self-aligning process for whole-wafer tunnel junction fabrication

The authors have developed a processing method for whole-wafer tunnel junctions which allows the preparation of planar tunnel junctions with just two lithographic steps and largely eliminates the inherent capacitance and potential failure problems associated with overlap between the base electrode and the counterelectrode metallization common to all existing methods. The basic feature of this self-aligning whole-wafer (SAWW) process is that the pattern used to create the counterelectrode metallization also defines the junction area. Results of preliminary trials of this method are presented and possible future developments discussed