Block implementation of a recursive least squares estimation algorithm

Author

Iiguni, Youji ; Sakai, Hideaki ; Tokumaru, Hidekatsu

Author_Institution

Fac. of Eng., Kyoto Univ., Japan

Volume

36

Issue

10

fYear

1988

fDate

10/1/1988 12:00:00 AM

Firstpage

1671

Lastpage

1675

Abstract

A block implementation of a Schur-type algorithm for the recursive least-squares problem using parallel processors is described. The parallel architecture can simultaneously process block data in one hardware clock cycle with regularly and locally connected processing elements. Such a computing structure is desirable for VLSI implementation. Moreover, a latency penalty is on the order of the block size and the filter order, which is small as compared to the previous results

Keywords

VLSI; estimation theory; filtering and prediction theory; least squares approximations; parallel algorithms; parallel architectures; Schur-type algorithm; VLSI implementation; block data; block implementation; hardware clock cycle; latency penalty; parallel architecture; parallel processors; processing elements; recursive least squares estimation algorithm; Adaptive filters; Adaptive signal processing; Clocks; Convergence; Digital filters; Finite impulse response filter; H infinity control; Least squares approximation; Signal processing algorithms; Speech processing;

fLanguage

English

Journal_Title

Acoustics, Speech and Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

0096-3518

Type

jour

DOI

10.1109/29.7557

Filename

7557