Title :
Block implementation of a recursive least squares estimation algorithm
Author :
Iiguni, Youji ; Sakai, Hideaki ; Tokumaru, Hidekatsu
Author_Institution :
Fac. of Eng., Kyoto Univ., Japan
fDate :
10/1/1988 12:00:00 AM
Abstract :
A block implementation of a Schur-type algorithm for the recursive least-squares problem using parallel processors is described. The parallel architecture can simultaneously process block data in one hardware clock cycle with regularly and locally connected processing elements. Such a computing structure is desirable for VLSI implementation. Moreover, a latency penalty is on the order of the block size and the filter order, which is small as compared to the previous results
Keywords :
VLSI; estimation theory; filtering and prediction theory; least squares approximations; parallel algorithms; parallel architectures; Schur-type algorithm; VLSI implementation; block data; block implementation; hardware clock cycle; latency penalty; parallel architecture; parallel processors; processing elements; recursive least squares estimation algorithm; Adaptive filters; Adaptive signal processing; Clocks; Convergence; Digital filters; Finite impulse response filter; H infinity control; Least squares approximation; Signal processing algorithms; Speech processing;
Journal_Title :
Acoustics, Speech and Signal Processing, IEEE Transactions on
