DocumentCode :
1494265
Title :
Effective Edge Width for 65-nm pMOSFETs and Their Variations Under CHC Stress
Author :
Wang, Mu-Chun ; Hsieh, Zhen-Ying ; Liao, Ching-Sung ; Tu, Chia-Hao ; Chen, Shuang-Yuan ; Huang, Heng-Sheng
Author_Institution :
Dept. of Electron. Eng., Ming-Hsin Univ. of Sci. & Technol., Hsinchu, Taiwan
Volume :
32
Issue :
5
fYear :
2011
fDate :
5/1/2011 12:00:00 AM
Firstpage :
584
Lastpage :
586
Abstract :
The narrow-width W effect of metal-oxide-semiconductor field-effect transistors (MOSFETs) with shallow trench isolation technology has been widely reported. The factor of most concern is the edge width Δw affecting the electrical characteristics of the MOSFETs. In this letter, the negative variation value of Δw, as explained in the content, was derived from 65-nm node p-channel MOSFETs (pMOSFETs). To verify the validity of Δw, the pMOSFETs were stressed by channel-hot-carrier stress conditions. According to the experimental results, the device parameter degradation, i.e., the threshold voltage VTH, was obviously dominated by |Δw|/W, and the degradation of the narrow-width device was also increased for the wide width.
Keywords :
MOSFET; hot carriers; isolation technology; CHC stress; channel-hot-carrier stress condition; device parameter degradation; edge width; electrical characteristics; metal-oxide-semiconductor field-effect transistor; narrow-width device; negative variation value; node p-channel MOSFET; pMOSFET; shallow trench isolation technology; size 65 nm; threshold voltage; Degradation; Hot carriers; Logic gates; MOSFETs; Resistance; Stress; Threshold voltage; Channel hot carrier (CHC); metal–oxide–semiconductor field-effect transistors (MOSFETs); narrow-width effect; shallow trench isolation (STI);
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/LED.2011.2109696
Filename :
5750027
Link To Document :
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