Title :
Compact test generation for full scan sequential circuits using multiple frame vectors
Author_Institution :
Sch. of Electron. & Electr. Eng., Kyungpook Nat. Univ., Taegu
fDate :
2/4/1999 12:00:00 AM
Abstract :
A new test set compaction method that uses multiple frame vectors to test fully scanned sequential circuits is proposed. The FAN algorithm is extended to generate compact multiple frame test vectors. The proposed method generates the smallest test sets among all recognised full scan test set compaction algorithms
Keywords :
logic testing; sequential circuits; FAN algorithm; compaction algorithm; full scan sequential circuit; multiple frame vectors; test generation;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19990145
