Title :
High performance square rooting circuit using hybrid radix-2 adders
Author :
Corsonello, P. ; Perri, S.
Author_Institution :
Dept. of Electron. Eng. & Appl. Math., Univ. of Reggio Calabria, Italy
fDate :
2/4/1999 12:00:00 AM
Abstract :
A new high performance bit parallel architecture for computing square roots is proposed. The architecture implements a non-restoring algorithm and is structured as a pipelined cellular array. To improve the performance, hybrid radix-2 adders are used. However, the conventional two´s complement representation for both the radicand and square root is maintained
Keywords :
digital arithmetic; bit parallel architecture; hybrid radix-2 adder; nonrestoring algorithm; pipelined cellular array; square rooting circuit;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19990178
