• DocumentCode
    1494695
  • Title

    High performance square rooting circuit using hybrid radix-2 adders

  • Author

    Corsonello, P. ; Perri, S.

  • Author_Institution
    Dept. of Electron. Eng. & Appl. Math., Univ. of Reggio Calabria, Italy
  • Volume
    35
  • Issue
    3
  • fYear
    1999
  • fDate
    2/4/1999 12:00:00 AM
  • Firstpage
    185
  • Lastpage
    186
  • Abstract
    A new high performance bit parallel architecture for computing square roots is proposed. The architecture implements a non-restoring algorithm and is structured as a pipelined cellular array. To improve the performance, hybrid radix-2 adders are used. However, the conventional two´s complement representation for both the radicand and square root is maintained
  • Keywords
    digital arithmetic; bit parallel architecture; hybrid radix-2 adder; nonrestoring algorithm; pipelined cellular array; square rooting circuit;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19990178
  • Filename
    755905
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1494695