Title :
A high-density DRAM cell with built-in gain stage
Author :
Kamoulakos, George ; Tsiatouhas, Yiorgos ; Chrisanthopoulos, Angelos ; Arapoyanni, Angela
Author_Institution :
Adv. Silicon Solution Group, Integrated Syst. Dept. S.A., Athens, Greece
fDate :
6/1/2001 12:00:00 AM
Abstract :
A high-density DRAM cell is proposed with a built-in vertical gain device topology. Due to the vertical built-in gain device, this cell exhibits increased reading speed, elongated refresh period, low-power oriented operation, and minor layout area penalty
Keywords :
DRAM chips; MOS memory circuits; cellular arrays; integrated circuit modelling; low-power electronics; built-in gain stage; elongated refresh period; high-density DRAM cell; layout area penalty; low-power oriented operation; reading speed; vertical gain device topology; Capacitance; Capacitors; Informatics; Performance gain; Random access memory; Semiconductor device modeling; Semiconductor devices; Semiconductor memory; Silicon; Topology;
Journal_Title :
Electron Devices, IEEE Transactions on
