Impact of CMOS processing steps on the drain current kink of NMOSFETs at liquid helium temperature

The impact of certain CMOS processing steps on the drain current kink in nMOSFETs fabricated in a 0.7-μm technology and operated at liquid helium temperatures (LHTs) is investigated, The kink is successfully suppressed when implementing a lightly-doped drain (LDD) or a p-well, while the application of a threshold voltage adjust implantation has a more subtle effect. In order to understand the observations in more detail the impact ionization rate in the different splits is analyzed, whereby particular efforts are spent to accurately determine the saturation drain voltage V_DSAT from the 4.2 K output characteristics. An optimized method based on the extrapolation of the output resistance yields consistent data and a critical field for inversion layer velocity saturation of (1.2±0.1)×10⁴ V/cm at 4.2 K. It is finally demonstrated that a high-energy room-temperature proton irradiation has a qualitatively similar beneficial effect on the kink as the use of an LDD, for example