DARSI: RC data reduction [VLSI simulation]

Author

Vanoostende, Paul ; Six, Paul ; De Man, Hugo J.

Author_Institution

IMEC, Leuven, Belgium

Volume

10

Issue

4

fYear

1991

fDate

4/1/1991 12:00:00 AM

Firstpage

493

Lastpage

500

Abstract

Taking into account RC effects in VLSI simulation and verification systems, without seriously degrading their efficiency, requires preliminary data reduction. A tool, DARSI (data reduction system for interconnects), that can handle both polysilicon and diffusion resistive effects is presented. It contains the reduction scheme described by S.-L. Su et al. (Proc. IEEE Conf. Computer-Aided Design, p.270-3, 1986), a novel line-based reduction method, a novel loop reduction scheme, and a technique for identifying important diffusion resistors. The number of parasitic elements is considerably reduced, while guaranteeing delay errors to be less than a few percent. DARSI is implemented in a general-purpose rule-based verification environment for VLSI and has a nearly linear complexity. Application to several practical designs is also discussed

Keywords

VLSI; circuit analysis computing; integrated circuit technology; DARSI; RC data reduction; RC effects; VLSI simulation; diffusion resistive effects; diffusion resistors; interconnects; line-based reduction method; loop reduction scheme; nearly linear complexity; polysilicon resistive effects; rule-based verification environment; Circuit simulation; Data mining; Degradation; Delay; Diodes; Feeds; Integrated circuit interconnections; Resistors; Very large scale integration; Wire;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.75632

Filename

75632