Title :
Chip design of memory-architecture-based minimum-classification-error
Author :
Gin-Der Wu ; Zhen-Wei Zhu ; Yung-Ti Chang
Author_Institution :
Dept. of Electr. Eng., Nat. Chi Nan Univ., Puli, Taiwan
Abstract :
This paper proposes the chip design of memory-architecture-based minimum-classification-error (MCE). The major contribution is of this MCE chip is to increase the discriminative capability rather than to fit the distribution of data in the application of classification problems. It includes matrix-function, exponent, logarithm, sigmoid function, and square-root. To implement MCE, UMC 90nm standard cell-library is adopted. The chip area is 8.07mm2, and the power consumption is 3.6393mW. The maximum operating frequency is 83MHz.
Keywords :
integrated circuit design; memory architecture; microprocessor chips; pattern classification; MCE chip design; Sigmoid function; UMC 90nm standard cell-library; classification problems; discriminative capability; exponent; logarithm; matrix-function; memory-architecture-based minimum-classification-error; square-root; Conferences; Decision support systems; Information processing; Intelligent sensors; discriminative capability; memory-architecture; minimum-classification-error (MCE);
Conference_Titel :
Intelligent Sensors, Sensor Networks and Information Processing (ISSNIP), 2014 IEEE Ninth International Conference on
Conference_Location :
Singapore
Print_ISBN :
978-1-4799-2842-2
DOI :
10.1109/ISSNIP.2014.6827587
