Title :
Effective synthesis algorithm for partitioned bus architecture
Author :
Jeon, Jinhwan ; Choi, Kiyoung
Author_Institution :
Dept. of Electr. Eng., Seoul Nat. Univ., South Korea
fDate :
3/18/1999 12:00:00 AM
Abstract :
An effective synthesis algorithm is proposed for partitioned bus architecture when the number of buses is constrained. In the proposed algorithm, the probability of bus conflict is reduced, leading to a performance improvement. Experimental results show ~10-50% performance improvement over the conventional method
Keywords :
circuit layout CAD; high level synthesis; integrated circuit interconnections; integrated circuit layout; logic partitioning; IC layout; bus conflict probability; constrained bus number; high level synthesis; partitioned bus architecture; synthesis algorithm;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19990331
