• DocumentCode
    1495575
  • Title

    Effective synthesis algorithm for partitioned bus architecture

  • Author

    Jeon, Jinhwan ; Choi, Kiyoung

  • Author_Institution
    Dept. of Electr. Eng., Seoul Nat. Univ., South Korea
  • Volume
    35
  • Issue
    6
  • fYear
    1999
  • fDate
    3/18/1999 12:00:00 AM
  • Firstpage
    440
  • Lastpage
    441
  • Abstract
    An effective synthesis algorithm is proposed for partitioned bus architecture when the number of buses is constrained. In the proposed algorithm, the probability of bus conflict is reduced, leading to a performance improvement. Experimental results show ~10-50% performance improvement over the conventional method
  • Keywords
    circuit layout CAD; high level synthesis; integrated circuit interconnections; integrated circuit layout; logic partitioning; IC layout; bus conflict probability; constrained bus number; high level synthesis; partitioned bus architecture; synthesis algorithm;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19990331
  • Filename
    756377
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1495575