Area-Efficient Prefilter Architecture for a CDMA Receiver

This brief proposes an area-efficient memory-based prefilter delay line structure. A prefilter-rake chip-level equalizer is used in a code-division multiple-access receiver to deal with multiple-access interference. A prefilter, which functions as an adaptive filter, has a sparsity property, where the number of taps with nonzero coefficients is much smaller than the number of whole taps. On the basis of the sparsity property, this brief shows how a memory device can be a reasonable candidate for a prefilter delay line. After proposing a scheme to reduce the area of the memory-based delay line, this brief shows that the proposed structure provides less area than a conventional register-based structure in typical industrial cases.