Within-Layer Overlay Impact for Design in Metal Double Patterning

In double patterning lithography (DPL), overlay errors between two patterning steps of the same layer translate into CD variability. Since CD uniformity budget is very tight, meeting requirement of overlay control is one of the biggest challenges for deploying DPL. In this paper, we electrically evaluate overlay errors for back-end-of-line DPL with the goal of studying relative effects of different overlay sources and interactions of overlay control with design parameters. Experimental results show the following: 1) the expected electrical impact of overlay in a path is not significant (<; 6% worst-case RC variation) and should be the basis for determining overlay budget requirement; 2) the worst-case electrical impact of overlay in a single line remains a serious concern (up to 16.6% ΔRC and up to 50 mV increase of peak crosstalk noise); 3) translational overlay error has the largest electrical impact compared to other overlay sources; and 4) overlay in y direction (x for horizontal metallization) has negligible electrical impact and, therefore, preferred routing direction should be taken into account for overlay sampling and alignment strategies. Design methods for reducing overlay electrical impact in wires are then identified. Finally, we explore positive/negative process options from an electrical perspective and conclude that positive process is preferred.